Chalcogenide Semiconductor Lab

2010 Patents 4

4

“Multi-level cell phase change memory devices having controlled resistance-drift parameter, memory systems employing such devices and methods of reading memory devices”

2023-08-24

Chang-Wook Jeong, Hyeong-Jun Kim, Dae-Hwan Kang, Seung-Pil Ko, Dong-Won Lim, “Multi-level cell phase change memory devices having controlled resistance-drift parameter, memory systems employing such devices and methods of reading memory devices” UP079,886 Samsung Electronics Co. Ltd. 2008 (US 07701749) 2010.04.20.

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3

“Multiple level cell phase-change memory devices having post-programming operation resistance drift saturation, memory systems employing such devices and methods of reading memory devices”

2023-08-24

Chang Wook Jeong (Seoul, KR) Dae-Hwan Kang (Seoul, KR) Hyeong-Jun Kim (Seoul, KR) Jae-Min Shin (Suwon-Si, KR) Seung-Pil Ko (Suwon-Si, KR) Assignees: SAMSUNG ELECTRONICS CO., LTD “Multiple level cell phase-change memory devices having post-programming operation resistance drift saturation, memory systems employing such devices and methods of reading memory devices” Samsung Electronics Co. Ltd. (US 07778079) 2010. 08.17

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2

“PHASE CHANGE MEMORY CELL WITH TRANSPARENT CONDUCTING OXIDE FOR ELECTRODE CONTACT MATERIAL”

2023-08-24

Byung-ki Cheong, Jeung-hyun Jeong, Dae-Hwan Kang, Taek Sung Lee, In Ho Kim, Kyung Seok Lee, Won Mok Kim, Ki-Bum Kim, Dong-Ho Ahn, “PHASE CHANGE MEMORY CELL WITH TRANSPARENT CONDUCTING OXIDE FOR ELECTRODE CONTACT MATERIAL” Korea Institute of Science and Technology (US 07851828) 2010.12.14

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1

“Non-Volatile Electrical Phase Change Memory Device Comprising Interfacial Control Layer And Method For The Preparation Thereof”

2023-08-24

Dae-Hwan Kang, In-Ho Kim, Byung-ki Cheong, Jeung-Hyun Jeong, Taek Sung Lee, Won Mok Kim, Ki-Bum Kim, “Non-Volatile Electrical Phase Change Memory Device Comprising Interfacial Control Layer And Method For The Preparation Thereof” Korea Institute of Science and Technology (US 07851778) 2010.12.14

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4 “Multi-level cell phase change memory devices having controlled resistance-drift parameter, memory systems employing such devices and methods of reading memory devices”

3 “Multiple level cell phase-change memory devices having post-programming operation resistance drift saturation, memory systems employing such devices and methods of reading memory devices”

2 “PHASE CHANGE MEMORY CELL WITH TRANSPARENT CONDUCTING OXIDE FOR ELECTRODE CONTACT MATERIAL”

1 “Non-Volatile Electrical Phase Change Memory Device Comprising Interfacial Control Layer And Method For The Preparation Thereof”

4

“Multi-level cell phase change memory devices having controlled resistance-drift parameter, memory systems employing such devices and methods of reading memory devices”

3

“Multiple level cell phase-change memory devices having post-programming operation resistance drift saturation, memory systems employing such devices and methods of reading memory devices”

2

“PHASE CHANGE MEMORY CELL WITH TRANSPARENT CONDUCTING OXIDE FOR ELECTRODE CONTACT MATERIAL”

1

“Non-Volatile Electrical Phase Change Memory Device Comprising Interfacial Control Layer And Method For The Preparation Thereof”