Address
Dep. of Semiconductor Engineering, POSTECH 77,
Cheongam-ro, Nam-Gu, Pohang, Gyeongbuk-Do, Korea
(37673)
TEL: +82-54-279-7085
E-mail: daehwankang@postech.ac.kr
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Copyright ⓒ 2023. Chalcogenide Semiconductor Lab (CSL)
All rights reserved | Designed by greypixel
Address
Dep. of Semiconductor Engineering, POSTECH 77, Cheongam-ro, Nam-Gu, Pohang, Gyeongbuk-Do, Korea (37673)
TEL: +82-54-279-7085
E-mail: daehwankang@postech.ac.kr
Copyright ⓒ 2023. Chalcogenide Semiconductor Lab (CSL) All rights reserved | Designed by greypixel
D. H. Kang, J.S. Kim, Y.R. Kim, Y.T. Kim, M.K. Lee, Y.J. Jun, J.H. Park, F. Yeung, C.W. Jeong, J. Yu, J.H. Kong, D.W. Ha, S.A. Song, J. Park, Y.H. Park, Y.J. Song, C.Y. Eum, K.C. Ryoo, J.M. Shin, D.W. Lim, S.S. Park, J.H. Kim, W.I. Park, K.R. Sim, J.H. Cheong, J.H. Oh, J.H. Park, J.I. Kim, Y.T. Oh, K.W. Lee, S.P. Koh, S.H. Eun, N.B. Kim, G.H. Koh, G.T. Jeong, H.S. Jeong, and Kinam Kim. “Novel heat dissipating cell scheme for improving a reset distribution in a 512M phase-change random access memory” IEEE Technical Digest of Symposia of 2007 VLSI Technologies and Circuits (June 14 – 16, Kyoto, Japan) pp. 96 – 97 (2007).