Address
Dep. of Semiconductor Engineering, POSTECH 77,
Cheongam-ro, Nam-Gu, Pohang, Gyeongbuk-Do, Korea
(37673)
TEL: +82-54-279-7085
E-mail: daehwankang@postech.ac.kr
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Copyright ⓒ 2023. Chalcogenide Semiconductor Lab (CSL)
All rights reserved | Designed by greypixel
Address
Dep. of Semiconductor Engineering, POSTECH 77, Cheongam-ro, Nam-Gu, Pohang, Gyeongbuk-Do, Korea (37673)
TEL: +82-54-279-7085
E-mail: daehwankang@postech.ac.kr
Copyright ⓒ 2023. Chalcogenide Semiconductor Lab (CSL) All rights reserved | Designed by greypixel
K. C. Ryoo, Y. J. Song, J. M. Shin, S. S. Park, D. W. Lim, J. H. Kim, W. I. Park, K.-R. Sim, J. H. Jeong, D. H. Kang, J. H. Kong, C. W. Jeong, J. H. Oh, J. H. Park, J. I. Kim, Y. T. Oh, J. S. Kim, S. H. Eun, S. P. Go, K. W. Lee, Y. Fai. J. Park, S. A. Song, G. H. Koh, R. H. Kim, H. S. Lim, G. T. Jeong, and K. Kim “Ring contact electrode process for high density phase change random access memory” Jpn J. Appl. Phys. Vol. 46, No.4B, pp. 2001 – 2005 (2007.4).